1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and a semiconductor device.
Priority is claimed on Japanese Patent Application No. 2007-74149, filed Mar. 22, 2007, the content of which is incorporated herein by reference.
2. Description of Related Art
In recent years, large scale integration (hereinafter LSI) has been adopted for the main components of computers and electrical appliances, in which a plurality of MOS transistors and resistors and the like are integrated on one chip.
Even in LSI, for example rapid miniaturization is proceeding in elements such as DRAM (Dynamic Random Access Memory).
FIG. 10 shows a cross-sectional mimetic diagram of a MOS transistor that constitutes a DRAM memory cell.
As shown in FIG. 10, an STI (Shallow-Trench Isolation) element isolation region 101 is formed at a predetermined region on the surface of a semiconductor substrate 100. Also, a P-well layer 102 that is adjacent to the element isolation region 101 is formed in the semiconductor substrate 100. A gate insulating film 103 that consists of silicon oxide is formed on the P-well layer 102 of the semiconductor substrate 100, and on that for example is formed a gate electrode 104 that consists of laminating a P-type polysilicon layer 104a and a metal layer 104b such as W. Then, a silicon nitride film 105 is formed so as to cover the gate electrode 104 and end portions 103a of the gate insulating film 103. A source-drain diffusion layer 106 is formed in the semiconductor substrate 100 adjacent to the gate electrode 104.
An interlayer insulating film 107 that consists of silicon oxide is for example formed so as to cover the semiconductor substrate 100 and the silicon nitride film 105, and the surface of the interlayer insulating film 107 is made flat by chemical mechanical polishing (CMP). Furthermore, a contact hole 107a is provided in the interlayer insulating film 107 by dry etching. A contact plug 110 which consists of a high melting point metal etc. is filled in the contact hole 107a, and this contract plug 110 is connected to the source-drain diffusion layer 106.
The source-drain diffusion layer 106 is formed by implanting an N-type impurity in the P-well layer 102 of the semiconductor substrate 100 by an ion implanting method. At this time, the implanted N-type impurity diffuses in the semiconductor substrate 100 and extends to the underside of the end portions 103a of the gate insulating film 103. In this way, an overlap region OL of the gate and the drain is formed in the semiconductor device shown in FIG. 10.
As a method for forming the silicon nitride film 105, the chemical vapor deposition (CVD) method using a mixed gas in which silane (SiH4), dichlorosilane (SiH2Cl2), ammonia (NH3), nitrogen (N2), hydrogen (H2), etc, are suitably nixed as a reactant gas is commonly known, and is often employed. In the silicon nitride film 105 that is formed with the CVD method, hydrogen atoms are contained, and so Si—H bonds exist stemming from these hydrogen atoms (refer to Japanese Unexamined Patent Application, First Publication, (JP-A) No. 2005-302892).
As shown in FIG. 10, in the state of the silicon nitride film 105 that includes the Si—H bonds being connected to the end portions 103a of the gate insulating film 103, cases of hydrogen atoms desorbing from the silicon nitride film 105 arise. When desorption of hydrogen atoms occurs, the leakage current in the overlap region OL of the gate and the drain increases, and so there has been a risk of the retention of information “1” and reliability of the DRAM decreasing.
The present invention was achieved in view of the above circumstances, and has as its object to provide a semiconductor device that has excellent retention of information “1” and reliability of the DRAM, and a manufacturing method thereof.